Bibliothèque de L'IMIST/CNRST

This book takes the reader through the actual manufacturing process of making a typical chip, from start to finish, including a detailed discussion of each step, in plain language. The evolution of today's technology is added to the story, as seen through the eyes of the engineers who solved some of the problems. The authors are well suited to that discussion since they are three of those same engineers. They have a broad exposure to the industry and its technology that extends all the way back to Shockley Laboratories, the first semiconductor manufacturer in Silicon Valley. The CMOS (Complementary Metal-Oxide-Semiconductor) process flow is the focus of the discussion and is covered in ten chapters. The vast majority of chips made today are fabricated using this general method. In order to ensure that all readers are comfortable with the vocabulary, the first chapter carefully and clearly introduces the science concepts found in later chapters. A chapter is devoted to pointing out the differences in other manufacturing methods, such as the gallium arsenide technology that produces chips for cell phones. In addition, a chapter describing the nature of the semiconductor industry from a business perspective is included. "The entire process of making a chip is surprisingly easy to understand. The part of the story that defies belief is the tiny dimensions: the conducting wires and other structures on a chip are more than a hundred times thinner than a hair - and getting thinner with every new chip design." * Included CD gives the reader a much greater comprehension of the process than a strictly print book with static illustrations provides * Authors are actual engineers who have a broad range of exposure and experience with chip technology * Contains a unique chapter describing the nature of the semiconductor industry from a business perspective.

CH 1: IC Fabrication Overview / CH 2: Support Technologies / CH 3: Forming Wells / CH 4: Isolate Active Areas (Shallow Trench Isolation) / CH 5: Building the Transistors / CH 6: First Level Metallization / CH 7: Multilevel Metal Interconnects and Dual Damascene / CH 8: Test and Assembly / APPENDIX A: Science Overview / APPENDIX B: Plasma Etch Supplement to Chapter 4.

Includes bibliographical references and index.

IC fabrication overview -- Introduction -- Support technologies -- Integrated circuit fabrication -- Test and assembly -- Summary -- Support technologies -- Introduction -- Contamination control -- Crystal growth and wafer preparation -- Circuit design -- Photomask and reticle preparation -- Forming wells -- Introduction -- Initial oxidation -- Photolithography -- Ion implantation -- Isolate active areas (shallow trench isolation) -- Introduction to shallow trench isolation -- Pad oxide growth -- Silicon Nitride deposition -- Photolithography for photo/etch -- From trenches in silicon dioxide -- Chemical mechanical polishing (CMP) to remove excess dioxide -- Wet etch removal of Silicon Nitride and pad oxide -- Building the transistors -- Introduction -- Thin film formation -- Poly gate formation -- Source/drain formation -- Salicide formation -- First level metallization -- Introduction -- Nitride and oxide depositions -- CMP planarization -- Photo/etch for contact holes -- Tungsten plug process -- Low-k dielectric process -- Copper first level interconnection process -- Multilevel metal interconnects and dual damascene -- Introduction -- Deposit barrier layer and intermetal dielectric -- Dual damascene process -- Form bonding pads -- Final passivation process -- Test and assembly -- Introduction -- Wafer and chip testing -- Assembly and packaging.

Includes CD-ROM.

Description based on print version record.